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How failure occurs is the first key question leading to an understanding of reliability. At TriQuint, failures are considered to be an essential part of each reliability study. Failures are required to identify root causes of reliability problems, or to evaluate the weakest link of an IC so that improvements can be leveraged for the best impact on reliability. Failures also provide the reference point for future comparisons. If subsequent tests are run before and after a process change, and they both result in zero failures, there's no way to decide if the process change improved or impaired the reliability. Most importantly: without a failure, a failure distribution cannot be determined. It's auspicious that the TriQuint data base contains over 10,000 failures from the various accelerated tests and engineering evaluations. However, just 'any old failure' won't do, however.

The primary failure mechanism for MesFET and pHEMT ICs manufactured at TriQuint is "sinking gates." Sinking gates are caused by gate metal interdiffusion into the channel. This interdiffusion causes parametric shifts in several device parameters because the effective channel thickness is reduced. The largest change is decreased channel current so that parameter is typically used as the failure criteria. A 20% change in channel current is our definition of a MesFET failure. In addition to channel current changes in a FET with sinking gates, channel resistance increases and the magnitude of the voltage required to pinch-off a FET is reduced (this usually means pinch-offs are more positive). Sinking gates have never been catastrophic and they are self-limiting in a sense because as the channel current decreases so does the power in the FET and thus the temperature is lowered causing the gates sink more slowly. Eventually, we expect that the channel could be severed completely by the gate and become open, but this condition has never been reached. The sinking gate mechanism has been observed under various temperatures and biases, but degradation is accelerated by temperature without bias or RF drive.

We have observed the physical gate degradation using cross-sections formed with a Focused Ion Beam. The movement of the metal gate at the GaAs surface is dramatic after high temperature aging. Some metal voiding is also present in the degraded gate, because of the mass of material that has moved into the GaAs. Operation at the maximum rated temperature (150°C) would be expected to exceed 2,000 years before a 1dB change could be observed. This expected longevity of sinking gates is acceptable in terms of our reliability goals, and is not considered as a threat to device lifetimes under normal operating conditions. Although gate sinking can be induced by high temperature acceleration, it has not yet been observed under nominal use conditions.

Several other failure mechanisms have been investigated, but their onset in ICs is too slow to be observed compared to sinking gates. In order to measure various failure mechanisms, TriQuint began the study of various component parts of ICs on an individual basis. These parts are called elements. Element studies have been conducted since the very beginning of reliability testing at TriQuint in 1984. Elements are sometimes named "Technology Characterization Vehicles" (TCVs). In this discussion, the element and TCV terminology should be considered equivalent as definitions for individual interconnect lines, air bridges, implanted resistors, capacitors, nichrome resistors, and active FET or HBT structures that are used as the building blocks for integrated circuits. By breaking ICs into these individual parts, the failure mechanisms that uniquely effect each element are more easily studied. Following, are examples of other wear out failure mechanisms.

The failure mechanism for first layer interconnect begins with an interdiffusion mechanism. The interconnect is composed of a layered structure of titanium, platinum, and gold. When these metals interdiffuse, the resistance of the interconnect increases. Auger studies indicate that the metals intermix, and the whole stack becomes homogeneous. On a percentage basis, the resistance change can be as high as 250%. But on an absolute basis, a 50% change is roughly as much as the process window is wide, or 40 milli-ohms per square. If the life testing is conducted under bias, electromigration can eventually occur, which causes catastrophic open circuits.

Implanted resistors have been studied to evaluate ohmic contact failure mechanisms. Ohmic degradation mechanisms have been elusive. Implanted resistor degradation has been found to be caused by changes in the contact resistance. Failure analysis on degraded FETs has shown that ohmic metal does diffuse into the GaAs, but the physical diffusion seems to have a minimal effect electrically on the FET performance, especially compared to sinking gates. In general, ohmic annealing is beneficial to circuit performance.

The failure mechanism for plated gold interconnect and airbridges is electromigration. Under high current density stress, mass transport occurs because of the "electron wind" in the metallization. Voids form along the plated gold, and eventually the interconnect fuses open, the nitride passivation will crack, and molten gold will flow out of the failure site. Less than a 25% change in plated gold resistance has ever been observed before the catastrophic failure, and usually the pre-fusing degradation is negligible.

The failure mechanisms for capacitors is Time Dependent Dielectric Breakdown (TDDB). Many tests have been conducted to evaluate dielectric performance. Once the capacitor dielectric was changed to plasma deposited nitride in 1985, life test failures were non-existent. As the capacitor dielectric thickness was reduced from 2,000 angstroms to 500 angstroms, voltage acceleration testing became more and more effective. Several improvement efforts have reduced the defect density in capacitors and they are now approaching theoretical maximums for voltage breakdown and longevity under voltage stress.

In addition to the representative failures that are generated in accelerated life testing, there is another source of information on failure mechanisms: field returns. Historically, ElectroStatic Discharge (ESD) has been the leading cause of failure in the field. Recent design work to improve immunity combined with efforts to improve countermeasures in our customer's factories have reduced ESD as a percentage of all causes. Assembly defects, testing issues, and processing defects are other causes of field returns. Each of these causes are tracked on a quarterly basis, and leading causes are targeted for process improvement.

In summary, there are many possible scenarios which could cause failure in GaAs devices. ICs have been broken down into their component parts to investigate the most prominent factors. Metal interdiffusion is the most common wear out mechanism, and it occurs in GaAs contacts, interconnects, and resistors. Electromigration is the other common mechanism, and it occurs in interconnects and resistors. Several other failure mechanisms can be hypothesized, especially ones related to field failures and other overstress conditions like ESD. We have investigated some of these hypothesized mechanisms, and found that surface charge effects, leakage effects, ohmic contact degradation, burn-out, channel compensation, Schottky contact degradation, carrier diffusion, substrate via cracking, sidegating, gate electromigration, passivation cracking, interconnect-airbridge contact degradation, hydrogen-gate interdiffusion, capacitor dielectric breakdown, interlevel dielectric breakdown, and ohmic contact electromigration are NOT mechanisms that occur on TriQuint fabricated ICs with nominal designs at specified operating conditions.