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The most important environmental condition affecting GaAs devices is ElectroStatic Discharge (ESD). Characterization tests have been performed on elements and ICs using JEDEC JESD22-A114, which utilizes the Human Body Model JEDEC JESD 22-A115, Machine Model, and JEDEC JESD22-C101 Charged Device Model. During these characterizations, many 10,000s of pulses have been applied to various structures, and GaAs has been found to be sensitive to ESD. In general, results depend mainly on the physical size of the structure being tested. Larger structures are more robust than smaller structures. Elements are also more sensitive than ICs. Most ICs exhibit a damage threshold above 500 volts. The exceptions are ICs without protection circuitry that utilize special custom circuitry for absolutely optimum performance. In these sensitive devices, ESD thresholds were willingly sacrificed for premium performance. In contrast, some devices have minimum thresholds exceeding even 2000 volts. This level of ESD sensitivity places GaAs ICs approximately equal to state-of-the-art CMOS technology. If GaAs users are already employing precautions for CMOS device handling, there should be no additional requirements to accommodate GaAs devices.

The most interesting effects discovered during ESD characterization were the lack of cumulative and latent phenomenon on GaAs elements. For example, single MesFETs. In this example, any change in reverse breakdown was used as the most sensitive failure criteria. There was a distinct threshold found at 1050 volts. Because there were so many pulses applied to the sample to reach the threshold initially, the test was repeated on a virgin MesFET, starting at 800 volts instead of at 100 volts. The result was the same. A third virgin FET was started at 1,000 volts and the threshold was found to be the same, even if over 50 pulses were applied immediately below the damage point. Latent effects were examined in a similar experiment. Virgin MesFETs were pulsed 50 times at a level 50 volts below their damage thresholds and then life tested at 290°C. Degradation occurred as expected except that the devices subjected to the ESD pulses degraded slightly less than the control (un-zapped) sample.

Package reliability testing has involved other environmental evaluations of GaAs devices manufactured at TriQuint. In general, the environmental tests identified in JEDEC JESD22 have been utilized to measure ceramic package reliability and assess environmental performance. Those JESD22 tests have been completed for three types of packages without any indication of failures related to the GaAs or the GaAs circuits. Additional tests have been performed to evaluate the performance of GaAs in humid environments. This is of special interest since standard products are typically manufactured epoxy die attach and in some cases with epoxy-sealed packages or in plastic encapsulated packages. All of the elemental testing has been conducted in packages open to the atmosphere, and nitrogen gas has never been utilized in the high temperature chambers, including during wafer storage testing. This is just an indication of the immunity of GaAs devices. In addition to the standard 85/85, Pressure Cooker Tests, and moisture resistance tests, special internal moisture tests have been developed. During one test, combinations of extra water and extra epoxy were purposely induced inside the package cavity, and sealed in. Temperature cycling and bias cycling were then conducted. The devices were first cooled to -20°C in an unbiased mode. This step is used to condense all the moisture inside the package cavity. Then the device is powered and forced up to 85°C for a time period. The device is then unpowered and frozen again. One thousand cycles are completed, and then the devices are submitted for residual gas analysis of the cavity. Even though these digital devices had as much as 6% water inside the cavity, there were still no failures that occurred during the 1,000 condensation, freezing, and biasing cycles of this special test.